This invention relates to a technique for manufacturing a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique that may be effectively used to form an insulating film on a metal wiring.
Recently, a technique for making a laminated structure, formed of an element and wiring, has been developed concomitantly with high integration of an LSI. Though elements in such a structure are separated by an interlayer insulating film which is disposed therebetween, the problem of separation or breakage of the wiring due to the film stress of the conductive layer or interlayer insulating film, which constitutes an element or wiring of the laminate, has been revealed as the lamination has been developed.
More particularly, in the case where the process involves high temperature heat treatment after the interlayer insulating film is formed on the top of wiring, it has been found that such heat treatment causes an increased film stress and results in the problem of wiring separation or breakage.
For example, Japanese Published Unexamined Patent Application No. Hei 10(1998)-173049 discloses a technique in which a BPSG (Boro-Phosphate-silicate glass) film 83 is coated on the surface of a bit-line wiring layer by means of a CVD (Chemical Vapor Deposition) technique. Furthermore, this published patent application discloses a technique which involves the use of a HDP-SiO (High Density Plasma Silicon Oxide) film instead of a BPSG film, which allows the high temperature treatment in the forming process to be eliminated, whereby the thermal stress can be suppressed extremely.
Furthermore, Japanese Published Unexamined Patent Application No. Hei 11(1999)-243180 discloses a technique in which a third interlayer-insulating film, that serves to insulate between a bit-line 27 and a bottom electrode of a capacitor, is formed as a silicon oxide film by use of a plasma CVD technique, wherein a special film forming condition is employed.